Appeal No. 1999-0288
Application No. 08/538,071 Page 14
As per the use of a state register to house the PME bit
controlling the specific process, the examiner asserts (answer,
page 9) that such a variation would not affect the system's
ability to perform the monitoring functions described above. The
examiner adds that allowing a state register to store this PME
bit or information related to the control of the monitoring
process, as shown by Brantley, would not be detrimental to
Wibecan's system because it is clearly suggested by Wibecan's
disclosure that the PME is utilized to control the specific
process to be monitored.
From our review of Wibecan and Brantley, we find that as
admitted by the examiner (final rejection, page 4) Wibecan does
not disclose a performance monitoring bit in a machine state
register, and that neither Wibecan nor Brantley discloses a
second MMCR. Although Brantley discloses the use of a
Performance Monitor Chip (PMC) in each Processor-Memory Element
(PME); that there are up to 500 PMEs, and that each PMC (page
195) includes, inter alia, a status register which controls the
type of data to be collected, the frequency of collection, as
well as providing status about the data collection, we find that
Brantley does not teach or suggest a match on a selected event in
performance monitoring of a processing system where the match is
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