Appeal No. 1999-0288
Application No. 08/538,071 Page 17
matched based upon a logic level of a bit within a machine state
register within the processing system. Independent claim 38
similarly recites determining a logic level for at least one bit
of a machine state register and determining logic levels of a bit
set of a second MMCR. Independent claim 39 similarly recites
triggering counting when the selected event is matched based upon
a logic level of a bit within a machine state register within the
processing system. Independent claim 40 similarly recites
triggering counting when the effective address is matched based
upon a logic level of a bit within a machine state register
within the processing system.
Thus, we find that even if the teachings of Wibecan and
Brantley were combined, that appellants' claims would still not
be met, because the prior art references to Wibecan and Brantley
do not teach or suggest the claim limitations set forth, supra,
as the prior art would not have suggested the use of a
performance miitoring bit in a machine state register, nor the
claimed second MMCR.
The examiner bears the initial burden of establishing a
prima facie case of obviousness. The extensive arguments of the
examiner, even if we agreed with him from our own experience and
background knowledge of the art, are not a substitute for
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