Appeal No. 2002-1994
Application No. 09/364,449
access a data value from the units in the cache line (col. 2,
lines 53-61). Although Thatcher does not particularly mention
using a logic array, a series of circuitry including logic
gates, as shown in Figure 2, is used for addressing the cache
line and retrieving data values based on the provided address.
Therefore we agree with the Examiner that the claimed “logic
array” reads on the circuitry disclosed by Thatcher for
selecting a cache line and reading the data value stored therein
based on its address since the claim does not require any
particular type of logic array. Accordingly, the 35 U.S.C.
§ 102 rejection of claims 6 and 7 is sustained.
With respect to claim 11, Appellants provide the same
arguments as those provided for claim 4 (brief, page 12). For
the same reasons discussed above with respect to claim 4, we
sustain the 35 U.S.C. § 102 rejection of claim 11, as well as
claims 14 and 15 which are grouped therewith, over Thatcher.
Turning now to claim 17, Appellants argue that the claimed
“selecting a subset of said plurality of storage units” is not
taught by Thatcher (brief, page 13). In response, the Examiner
asserts that Thatcher does select a subset of the plurality of
storage units for output to the CPU regardless of the fact that
the entire line may be input to the formatter (answer, page 9).
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