Appeal No. 2003-0008
Application No. 09/174,936
decode stage of the pipelined processor and instructions with
false predicates are annulled before they are processed by
subsequent stages. According to Appellants (specification, pages
5 and 6), by eliminating unnecessary processing of false
predicate instructions in the later pipeline stages, such as the
execute and write-back stages which typically consume the most
power, the power consumption of the processor can be reduced.
Claim 1 is illustrative of the invention and reads as
follows:
1. A method of processing instructions in a processing
system, the method comprising the steps of:
evaluating a predicate of a predicated instruction in a
decode stage of a pipelined processor of the system; and
annulling the predicated instruction in the decode stage if
the predicate has a particular value.
The Examiner relies on the following prior art:
Martell 5,761,476 Jun. 02, 1998
Shiell et al. (Shiell) 5,799,180 Aug. 25, 1998
Claims 1-4, 6-13, and 15-20, all of the appealed claims,
stand finally rejected under 35 U.S.C. § 103(a) as being
unpatentable over Martell in view of Shiell.
Rather than reiterate the arguments of Appellants and the
Examiner, reference is made to the Brief (Paper No. 14 and the
Answer (Paper No. 15) for the respective details.
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