Appeal No. 2003-1315
Application No. 09/503,838
in the semiconductor chip using the stored parasitic capacitance
value.
Claim 1 is the only independent claim on appeal, and it
reads as follows:
1. A method for testing a semiconductor chip, the method
comprising:
providing a test structure and a dummy structure in the
semiconductor chip, wherein the dummy structure has a
structure that replicates the test structure except having a
discontinuity that disables the dummy structure;
coupling to the dummy structure and determining the
parasitic capacitance of the dummy structure; and
coupling to the test structure and analyzing the test
structure using the determined parasitic capacitance of the
dummy structure; and
storing the determined parasitic capacitance of the
dummy structure in a memory device, and wherein analyzing
the test structure using the determined parasitic
capacitance of the dummy structure includes accessing the
stored parasitic capacitance.
The references relied on by the examiner are:
Aeba 5,466,956 Nov. 14, 1995
Akram et al. (Akram) 6,022,750 Feb. 8, 2000
“Multi-Chip Probe Card for Capacitance Voltage Measurements,” IBM
Technical Disclosure Bulletin, Vol. 25, pp. 5736-37 (Apr. 1,
1983)(Hereinafter referred to as IBM TDB).
Olowolafe, “C-V Profiles,” Wiley Encyclopedia of Electrical and
Electronics Engineering Online, (Univ. of Del., Dec. 27, 1999).
2
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