Appeal No. 2003-1315
Application No. 09/503,838
semiconductor device which comprises the following steps:
providing a test structure A2 and a dummy structure A1 on a
semiconductor chip 9 where the dummy structure replicates the
test structure except for a discontinuity that disables the dummy
structure [column 4, lines 55-65], coupling to the dummy
structure and determining the parasitic capacitance Cy [column 5,
lines 25-30], coupling to the test structure and analyzing the
test structure using the known parasitic capacitance [column 5,
lines 30-37].” The examiner acknowledges (answer, page 4) that
“Aeba does not disclose the storing and accessing the stored
parasitic capacitance in a memory device.” Since Olowolafe
“teaches the use of a computer when making C-V measurements
[Figure 9],” the examiner concludes (answer, page 4) that “[i]t
would have been obvious to one of ordinary skill in the art to
store and access the store[d] parasitic capacitance in the method
of Aeba since computers are commonly used in C-V measurement
systems and since Aeba is directed towards analyzing the test
structure.”
Appellant argues (brief, page 6) that areas A1 and A2 are
not test and dummy structures, respectively, and that Aeba
neither teaches nor would have suggested to one of ordinary skill
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