Appeal No. 2003-1316
Application No. 09/430,531
Claim 1 is illustrative of the claimed invention, and it reads
as follows:
1. An integrated delay locked loop circuit for write
precompensation and clock recovery connected to receive source of
multiple clock signals, each of different relative phase,
comprising:
a plurality of clock selection multiplexers each connected to
receive said multiple clock signals; and
a control circuit connected to control each of said plurality
of clock selection multiplexers to pass a respective selected one
of said multiple clock signals to a clock selection output, wherein
if one clock selection multiplexer of said plurality of clock
selection multiplexers is selected to pass a particular one of said
clock signals to its clock selection output, all of the remaining
clock selection multiplexers of said plurality of clock selection
multiplexers are prevented from passing said particular one of said
clock signals to their respective clock selection outputs.
The reference relied on by the examiner is:
Hillis 5,485,627 Jan. 16, 1996
Claims 1 through 20 stand rejected under 35 U.S.C. § 102(b) as
being anticipated by Hillis.
Reference is made to the brief (paper number 18) and the
answer (paper number 19) for the respective positions of the
appellants and the examiner.
OPINION
We have carefully considered the entire record before us, and
we will sustain the anticipation rejection of claims 1 through 20.
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