Appeal No. 2003-1316
Application No. 09/430,531
Appellant argues (brief, page 5) that:
Hillis does not disclose or suggest the presently
claimed invention including if one clock selection
multiplexer of the plurality of clock selection
multiplexers is selected to pass a particular one of the
clock signals through the clock selection output all of
the remaining clock selection multiplexers of the
plurality of clock selection multiplexers are prevented
from passing the particular one of the clock signals to
their respective clock selection outputs as defined in
independent Claims 1, 8, 14 and 18.
The Examiner alleges that control circuit 400 and
multiplexer 430a and 430d discloses this aspect. There
is nothing in Hillis to disclose the conditional nature
of the above language.
The appellants’ arguments to the contrary notwithstanding, we
agree with the examiner’s assessment of the teachings of Hillis
(answer, pages 3 through 6). Hillis explicitly states (column 4,
lines 38 through 57) that the control means or status register 400
controls the multiplexers so as to connect the host computers and
the processors arrays as desired by the user by applying a
selection signal to the desired multiplexer “along with a no-
operation signal if no such connection is to be made.” Hillis
specifically states that “one” of the host computer 310A through
310D can be connected to “one” of the processor arrays 330A through
330D by selecting one multiplexer to pass signals from the host to
the array (column 5, lines 34 through 42; column 7, lines 19
through 23). Thus, if one multiplexer in the plurality of
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