Ex Parte HERRELL et al - Page 2

          Appeal No. 2003-1361                                                        
          Application No. 09/099,758                                                  
          circuit board vias and a first group of carrier vias to a first             
          side of the circuit carrier, and then through a second group of             
          carrier vias and a second group of circuit board vias.                      
               Claim 1 is illustrative of the claimed invention, and it               
          reads as follows:                                                           
               1.  An apparatus comprising:                                           
               an integrated circuit carrier including:                               
               first and second groups of carrier vias extending                      
          substantially from a first side of said carrier towards a second            
          side of said carrier;                                                       
               a circuit board including:                                             
               first and second groups of circuit board vias extending                
          substantially from a first side of said circuit board towards a             
          second side of said circuit board;                                          
               a loop circuit having a loop inductance, said loop circuit             
          defined from said first group of circuit board vias, through said           
          first group of carrier vias to said first side of said circuit              
          board and back through said second group of carrier vias, through           
          said second group of circuit board vias;                                    
               wherein said carrier vias of said first and second groups              
          are arranged in an anti-parallel tessellation and include a                 
          substantial majority of all carrier vias for coupling respective            
          power supply voltages; and                                                  
               wherein said circuit board vias of said first and second               
          groups are arranged in an anti-parallel tessellation and include            
          a substantial majority of all circuit board vias for coupling               
          respective power supply voltages.                                           
               The references relied on by the examiner are:                          
          Hernandez                     4,754,366      June  28, 1988                 
          Sudo et al. (Sudo)            5,475,264      Dec.  12, 1995                 
          Patil et al. (Patil)          5,672,911      Sept. 30, 1997                 
          Forehand et al. (Forehand)    5,847,936      Dec.   8, 1998                 
                                             (filed June 30, 1997)                    
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