Appeal No. 2003-1361
Application No. 09/099,758
Fig. 12 causes the decreasing of “unwanted inductance
present in the multilevel thin film wiring layers 22"
(column 5, lines 5-11). Accordingly, one skilled in
the art would [have] recognized that the loop circuit
arranged in Fig. 12 of Sudo et al would have properties
of reduction in the inductance because it has been held
that when the structure recited in the reference is
substantially identical to that of the claims, claimed
properties or functions are presumed to be inherent.
Appellants argue (brief, pages 8 and 12) that the power
supply vias taught by Sudo (Figures 11 and 12) are not in a loop
circuit as claimed, and that such a loop circuit is neither
expressly nor inherently disclosed in the applied references.
We agree with appellants’ arguments. We find that Sudo does
not disclose a loop circuit because the Figure 11 embodiment does
not show a connection between the ground pad electrode 16 and the
already connected LSI chip 23 and power supply pad electrode 15.
Thus, the appellants correctly argue (brief, pages 14 and 15)
that:
First, as a preliminary matter, no circuit
involving vias 15 and 16 is disclosed. Second, no
reasonable interpretation of FIG. 11 supports the
conclusion that such a circuit is necessarily inherent.
In fact, the reasonable interpretation of FIG. 11 is
that any complementary, opposing direction current that
would flow through a return circuit path . . . involves
a via well removed from via 15 . . . . However,
whatever the actual location, no reasonable
interpretation of FIG. 11 supports the argument that
via 16 is necessarily the return path. Accordingly,
Sudo simply does not disclose a loop circuit, as
claimed.
In view of the foregoing, the obviousness rejection of
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