Ex Parte HERRELL et al - Page 3

          Appeal No. 2003-1361                                                        
          Application No. 09/099,758                                                  
               Claims 1, 6 through 13, 16 and 52 through 54 stand rejected            
          under 35 U.S.C. § 103(a) as being unpatentable over Sudo in view of         
          Forehand.                                                                   
               Claims 2 through 5 stand rejected under 35 U.S.C. § 103(a) as          
          being unpatentable over Sudo in view of Forehand and Patil.                 
               Claims 14 and 15 stand rejected under 35 U.S.C. § 103(a) as            
          being unpatentable over Sudo in view of Forehand and Hernandez.             
               Reference is made to the brief (paper number 27) and the               
          answer (paper number 28) for the respective positions of the                
          appellants and the examiner.                                                
                                       OPINION                                        
               We have carefully considered the entire record before us,              
          and we will reverse the obviousness rejections of claims 1                  
          through 16 and 52 through 54.                                               
               The examiner has made findings (answer, page 1) that:                  
               [F]irst and second groups of carrier vias 54-1 and 54-2                
               [in Sudo] have an arrangement of multiple, parallel                    
               oriented conductive structures of the loop circuit, and                
               wherein current flows through a first group of the                     
               conductive structures is in an opposing direction to                   
               the current flow through a second group of the                         
               conductive structures.  It is noted that the loop                      
               circuit as disclosed in Fig. 12 of Sudo et al would be                 
               considered as a loop circuit having a loop inductance                  
               because the mutual loop inductance would be formed when                
               the current flow through the first and second groups of                
               complementary power carrier vias.                                      
          According to the examiner (answer, page 2):                                 
               Sudo et al do further disclose that the loop circuit of                
               the closest power vertical conductive paths 15 and 16                  
               arranged in Fig. 11 or the loop circuit arranged in                    
                                          3                                           




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