Appeal No. 2004-0317
Application No. 09/319,822
definition signal and displays the high-definition and converted
standard definition signals.
Representative independent claim 1 is reproduced as follows:
1. A digital processor having common architecture for
processing multiple format video signals, comprising:
an input network for receiving high definition formatted
video data and standard definition formatted video data;
a decoder coupled to said input network for producing high
definition decoded and decompressed data;
a converter coupled to said input network for converting
said standard definition formatted data to a format compatible
with said high definition formatted data;
a common memory for storing high definition and standard
definition formatted data during processing by said processor;
and
a display processor for processing said high definition
formatted data and said converted standard definition formatted
data for display.
The examiner relies on the following references:
Faroudja 5,754,248 May 19, 1998
Yasuki et al. (Yasuki) JP 408098105A April 12, 1996
Claims 1-14 stand rejected under 35 U.S.C. § 103 as
unpatentable over Yasuki and Faroudja.
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