Appeal No. 2004-0909 Page 2
Application No. 09/053,398
If a task is postponed or deferred, the relevant information about the task must be
restored when the task resumes its use of the processor. (Spec. at 1.)
The contents of registers determine the state of the processor for a particular
task. In particular, the Intel Architecture provides a rich set of registers including the
aliased floating-point (FP) and integer packed data registers. Although these registers
need to be saved during a task switch, the appellants opine that the conventional
method of doing so suffers at least three drawbacks. (Id.) First, because the format of
the saved data depends on the operating mode of the processor (e.g., protected mode,
real-address mode) and on the operand-size in effect (e.g., 16-bit, 32-bit), the saving
requires branching in microcode, which results in long processing time and inefficient
memory usage. Second, the saved data feature irregular address boundaries, which
creates inefficient memory allocation and increased software overhead. Third,
automatically initializing the FP unit by loading default values into associated registers
is time consuming and often unnecessary. (Id. at 2.)
According to the appellants’ invention, in contrast, saving the contents of
registers associated with the floating-point unit and packed data unit of a processor is
generic for all operational modes and operand sizes. The storing of the contents is
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