Appeal No. 2004-0909 Page 3
Application No. 09/053,398
aligned at 16-byte boundaries. In addition, a processor's state is saved without
initialization. Streamlining the data structure of the processor's state and eliminating
unnecessary operations, assert the appellants, reduces the time required to save and
restore the processor's state. (Id. at 5.)
A further understanding of the invention can be achieved by reading the following
claim.
1. A method comprising:
decoding a single instruction by a processor, said processor
capable of operating under a plurality of operational modes and operand
sizes;
in response to said decoding said single instruction
transferring contents of a plurality of registers associated with at
least a functional unit in the processor to a memory according to a
predetermined format into a plurality of groups of data, each group of data
being aligned at an address boundary which corresponds to a multiple of
2N bytes, the contents excluding instructions of the processor, the
predetermined format being constant for the plurality of operational modes
and operand sizes and defining a data structure including control word for
the at least functional unit; and
retaining the contents of the plurality of registers after said
transferring.
Claims 1-26 stand rejected under 35 U.S.C. § 103(a) as obvious over U.S.
Patent No. 5,410,682 ("Sites").
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