Appeal No. 2004-2095
Application No. 09/384,503
achieved.” See the specification, page 5, lines 20-22. Details of
this appealed subject matter are recited in claim 15 which is
reproduced below:
15. A method of fabricating an integrated circuit located on a
semiconductor wafer, comprising:
forming a doped base substrate;
forming an insulator layer on the doped base substrate; and
forming a doped ultra thin active layer on the insulator layer
to a thickness ranging from about 10nm to about 15 nm, the ultra
thin active layer including a gate oxide, a gate formed on the gate
oxide wherein a width of the gate oxide is coextensive with a width
of the gate; and source and drain regions formed in the ultra thin
active layer and adjacent the gate.
In support of his rejections, the examiner relies on the
following prior art references:
Yoshimi et al. (Yoshimi) 5,698,869 Dec. 16, 1997
Yamazaki et al. (Yamazaki) 6,323,072 B1 Nov. 27, 2001
The appellants’ admission at page 9 of the specification
referring to prior art Figure 1 in the application (hereinafter
referred to as “admitted prior art”).
The appealed claims stand rejected as follows:
(1) Claims 15, 17 through 19 and 21 under 35 U.S.C. § 103 as
unpatentable over the combined teachings of the admitted prior art
and Yamazaki; and
(2) Claim 20 under 35 U.S.C. § 103 as unpatentable over the
combined teachings of the admitted prior art, Yamazaki and Yoshimi.
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