Appeal No. 2004-2095
Application No. 09/384,503
We reverse.
The claimed method of fabricating an integrated circuit on a
semiconductor wafer as represented by claim 15 is admittedly known,
except for forming a doped ultra thin active layer having a
thickness ranging from about 10nm to about 15 nm on an insulator
layer. See the specification, pages 5 and 9. The admittedly known
method is directed to forming an active layer having a thickness
“typically [ranging] from about 600 nm to about 800 nm...” See the
specification, page 5.
To remedy this deficiency in the admittedly known integrated
circuit fabricating method, the examiner relies on the disclosure
of Yamazaki. See the Answer, pages 3-5. Yamazaki recommends
employing an active layer having a thickness falling “within a
range of from 20 to 30 nm, preferably at 24 nm” to reduce the tune-
off current in magnitude. See column 24, lines 52-57. However, as
correctly pointed out by the appellants (the Brief, page 7), this
active layer does not have a thickness which is inclusive of the
claimed thickness. Compare In re Sebek, 465 F.2d 904, 907, 175
USPQ 93, 95 (CCPA 1972)(“Where, as here, the prior art disclosure
suggests the outer limits of the range of suitable values, and that
the optimum resides within that range, and where there are
indications elsewhere that in fact the optimum should be sought
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