Appeal No. 2004-2095
Application No. 09/384,503
within that range, the determination of optimum values outside that
range may not be obvious.”). More importantly, this active layer
is said to be useful only in a case where a thermal oxide film of
20 nm is formed at the interface between the active layer and
silicon oxide layer and where a width of a gate oxide is not
coextensive with a width of a gate as urged by the appellants. See
Yamazaki, column 24, lines 52-55 and Figures 4A-4E, together with
the Brief, pages 8-11 and the Reply Brief, page 3.
The examiner also relies on the disclosure of Yoshimi. See
the Answer, page 6. However, it is relied upon to show that it is
well known to employ an insulating layer having the claimed
thickness. See the Answer, page 6. The examiner does not refer to
any teaching in Yoshimi to remedy the above deficiency. See the
Answer in its entirety.
Thus, we are constrained to agree with the appellants that the
applied prior art references as whole would not have led one of
ordinary skill in the art to form an active layer having the
claimed thickness during the admittedly known integrated circuit
fabrication method. Specifically, the examiner, on this record,
has not proffered sufficient evidence to demonstrate that the
claimed ultra thin active layer is useful for the known DRAM device
of the type discussed in the specification.
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