Appeal No. 2004-0636
Application No. 09/045,041
Appellant's invention relates to a method of carrying out
simulation of a circuit. The method simplifies simulation by
checking for partial circuits exhibiting equivalent operational
characteristics and compressing such operationally equivalent
partial circuits into one partial circuit. Claim 9 is
illustrative of the claimed invention, and it reads as follows:
9. A method of carrying out simulation of a circuit,
comprising:
inputting data comprising configurations for a plurality of
partial circuits, and connectional relationships for input and
output terminals of the partial circuits;
extracting, from the circuit to be simulated, the plurality
of partial circuits to inspect for equivalent operational
characteristics;
inspecting the plurality of partial circuits to detect
partial circuits exhibiting equivalent operational
characteristics, based on the configurations of the plurality of
partial circuits, and judging equivalence when the configurations
of said plurality of partial circuits are mutually consistent;
and
compressing the circuit by integrating the partial circuits
exhibiting equivalent operational characteristics into one
circuit and simulating the compressed circuit.
The prior art reference of record relied upon by the
examiner in rejecting the appealed claims is:
Chakrabarti et al., "An Improved Hierarchical Test Generation
Technique for Combinational Circuits with Repetitive Sub-
circuits," IEEE Proc Fourth Test Symp. 237-243 (1995)
(Chakrabarti)
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