Appeal No. 2004-1608
Application 09/752,873
The disclosed invention pertains to a method and
apparatus for accessing a cache memory.
Representative claim 5 is reproduced as follows:
5. A cache data access system, comprising:
a plurality of ways;
decoders coupled to each of said ways, wherein each
decoder is to find a data location in one said plurality of ways
based on an address;
a tag unit to compare said address with a tag array and
to generate a hit/miss signal; and
sense amplifiers coupled to each of said ways, wherein
one of said sense amplifiers is to read data from said data
location if it receives said hit/miss signal as a hit,
wherein said data read by the one of the sense
amplifiers is transmitted on a global bitline.
The examiner relies on the following references:
Brauer et al. (Brauer) 5,550,774 Aug. 27, 1996
Ayukawa et al. (Ayukawa) US2002/0118591 Aug. 29, 2002
(effective filing date of Aug. 16, 1999)
Claims 5, 6, 8-12 and 19-26 stand rejected under
35 U.S.C. § 103(a). As evidence of obviousness the examiner
offers Brauer in view of Ayukawa.
Rather than repeat the arguments of appellant or the
examiner, we make reference to the briefs and the answer for the
respective details thereof.
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