Appeal No. 2004-1608
Application 09/752,873
can be reduced [page 7, paragraphs 14-15]. Therefore, we agree
with the examiner that Ayukawa provides motivation for modifying
the cache of Brauer. Specifically, Ayukawa would have taught the
artisan that using global bitlines in Brauer would enable a
reduction in chip size which is always a desirable result in
integrated circuit devices.
With respect to claims 6, 9-11 and 25, which stand or
fall together, appellant argues that the examiner fails to make a
prima facie case of obviousness because the examiner fails to
identify what portions of the references are relied upon for the
combination of local sensing and subsequent global transmitting
by the sense amplifiers [brief, pages 5-6]. The examiner
responds that local sensing, local bitlines and global bitlines
are shown in Ayukawa [answer, page 7]. Appellant responds that
the examiner has failed to identify the pertinent portions of the
applied prior art with particularity [reply brief, page 3].
We will sustain the examiner’s rejection of claims 6,
9-11 and 25. As noted by the examiner, Ayukawa teaches in Figure
5 that local bitlines DL connect the sense amplifiers SA to the
various banks of memory. When the teachings of Ayukawa are
combined with the teachings of Brauer, the local bitlines would
-9-
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