Appeal No. 2004-1608
Application 09/752,873
motivation proposed by the examiner is based on hindsight gleaned
from appellant’s own disclosure [brief, pages 3-5].
With respect to claims 5, 8 and 21, which stand or fall
together [brief, page 2], appellant specifically argues that
there is no motivation to combine the references. The examiner
responds that Ayukawa clearly suggests that global bitlines are
desirable in cache devices for at least the reason of faster
accessing speed and reduction in circuitry and complexity
[answer, pages 5-7]. Appellant responds that the examiner has
not identified any motivation to combine the teachings of Brauer
and Ayukawa which comes from the references themselves [reply
brief, pages 1-3].
We will sustain the examiner’s rejection of claims 5, 8
and 21. Ayukawa teaches a cache memory in which a global bitline
is provided for four bitline pairs [page 5, paragraph 94].
Regardless of whether the cache memory of Ayukawa is an
associative cache or a direct cache, we find that Ayukawa teaches
that four bitlines of a cache can be connected to a single global
bitline. Note also that Ayukawa teaches how a plurality of sense
amplifiers can be connected to global bitlines [page 11,
paragraph 171]. Ayukawa also teaches that the global bitlines
can be disposed with respect to power lines so that the chip size
-8-
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