Appeal No. 2004-1716
Application 10/106,631
configuration registers. Claim 2 is illustrative:
2. A microcontroller, comprising:
an execution unit;
a peripheral device coupled to the execution unit, the
peripheral device comprising configuration registers; and
a means for defining a scan path comprising the
configuration registers and for communicating configuration data
for the peripheral device.
THE REFERENCE
Byers et al. (Byers) 5,168,555 Dec. 1, 1992
THE REJECTION
Claims 2-9 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Byers.
OPINION
We reverse the aforementioned rejection. We need to address
only the sole independent claim, i.e., claim 2.
Byers discloses (col. 4, lines 11-27):
The program information on bus 66 enters the controller
52 at unit support logic 68 and is applied to the scan
set logic 68 to provide output signals on line 69 for
setting the individual interface latches 71, 72 and 73
of the MSU [memory storage unit] to MSU interfaces A, B
and C. The signals circulate via lines 69 to the input
of partitioning register 75 and via line 76 to the
input of system status register 65. The return path of
the series scan set configuration signals is shown as
line return path 77. Once the latches representing the
partitioning register 75 bit positions and the system
2
Page: Previous 1 2 3 4 5 6 Next
Last modified: November 3, 2007