Appeal No. 2004-1716
Application 10/106,631
status register 65 bit positions are dynamically
established, then the scan set logic 68 informs the
system support processor 54. Then the information in
partitioning register 75 is transferred via bus 74 to
the input logic of latches 71, 72 and 73 to set the
interface latches.
The examiner argues that “Byers’s combine[d] teachings of
71-73, 68 & 75, as a single collective, teaches the above argued
claim limitations (e.g., ‘a means for defining a scan path
comprising the configuration registers and for communicating
configuration data for the peripheral device[’])”, and that “the
Byers- ‘interface latches 71, 72 and 73 of the MSU’
represents/equates the claimed ‘configuration registers’; and the
Byers - a collective combination of ‘77, 75 & 65’
represents/equates the claimed ‘means for defining a scan path
and for communicating configuration data for the peripheral
device’; and the Byers- ‘52’ MSU represents/equates the claimed
‘peripheral device’” (answer, page 5).
The appellants’ claim 2, however, does not only require a
peripheral device’s configuration registers and a means for
defining a scan path, but also requires that the scan path
comprises the configuration registers. As set forth above, Byers
discloses that after the scan path has been used to establish the
bit positions of partitioning register 75 and system status
3
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Last modified: November 3, 2007