Appeal No. 2004-1716
Application 10/106,631
register 65, then information in partitioning register 75 is
transferred via bus 74 to the input logic of interface
latches 71-73, which the examiner relies upon as corresponding to
the appellants’ configuration registers, to set those latches.
This disclosure indicates that latches 71-73 are not in the scan
path. The examiner has not provided evidence or reasoning to the
contrary, or explained how Byers would have fairly suggested, to
one of ordinary skill in the art, placing latches 71-73 in the
scan path.
Accordingly, we conclude that the examiner has not carried
the burden of establishing a prima facie case of obviousness of
the appellants’ claimed invention.
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