Appeal No. 2005-0123
Application No. 10/114,759
1. A method of fabricating an integrated circuit, comprising:
loading a semiconductor workpiece into a chamber;
providing a metallic source and a supply of nitrogen source
gas to the chamber;
depositing a conductive barrier layer on the workpiece
within the chamber, wherein the layer is formed from the metallic
source and the nitrogen source gas;
reducing continuously the supply of nitrogen source gas
while depositing the barrier layer, wherein the barrier layer
comprises a substantially pure metal sub-layer; and
electroplating a metal layer directly on a top surface of
the substantially pure metal sub-layer without an intervening
deposition on the semiconductor workpiece.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Simpson et al. (Simpson) 6,174,425 Jan. 16, 2001
(filed May 14, 1997)
Xu et al. (Xu) 6,217,721 Apr. 17, 2001
(filed Apr. 05, 1996)
Prior art relied upon by the Board is:
Admissions as to the prior art at page 2 of the specification
(appellant's admissions)
Claims 1 through 10 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Xu in view of Simpson.
Reference is made to the Examiner's Answer (mailed
April 22, 2004) for the examiner's complete reasoning in
support of the rejection, and to appellant's Brief (filed
2
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