Appeal No. 2005-0293
Application No. 09/727,139
providing a semiconductor substrate having a device
component layer thereon;
forming a hard mask to overlie the device component layer,
wherein the hard mask has first and second edges spaced by a
first lateral dimension;
forming reactable sidewall spacers on the hard mask; and
reacting the edge portions of the hard mask with the
reactable sidewall spacers to reduce the first lateral dimension
to a second lateral dimension. (Column 2, lines 53-63.)
Specifically, Xiang teaches a method including the steps
of:
forming a hard mask 22 of lateral dimension (D1) having a
portion 24 of first reaction layer 18 and a cap layer 26 of
reaction resistant layer 20 (column 4, lines 3-15; Fig. 3);
forming a second reaction layer 31 overlying the hard mask
22 (column 4, lines 16-18; Fig. 4);
carrying out an anisotropic etching process (preferably by
reactive ion etching or RIE) to form reactive sidewall spacers
33 and 35 adjacent to first and second edges 28 and 30 of
portion 24 of the hard mask 22 (column 4, lines 26-39; Fig. 5);
carrying out a chemical reaction such that, as the chemical
reaction proceeds, first and second edges 28 and 30 recede along
4
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Last modified: November 3, 2007