Appeal No. 2005-0293
Application No. 09/727,139
the surface of etch stop layer 16 to form a first reaction
product edge portion 32 and a second reaction product edge 34
and leave a residual layer 36 (column 4, lines 40-43; Fig. 6);
preferentially removing cap layer 26 (and preferably also
etch stop layer 16) (column 5, lines 4-25; Fig. 7);
selectively etching (by either a selective isotropic wet
etching process or a downstream isotropic plasma etching
process) first and second reaction product edge portions 32 and
34 (column 5, lines 27-45; Fig. 8); and
removing portions of etch stop layer 16 (by RIE) exposed by
residual layer 36 to form a hard mask 22 with reduced lateral
dimension (D2) (column 5, lines 46-67; Fig. 9).
Nakajima, the other relied upon prior art reference common
to all four rejections, discloses a method for manufacturing a
semiconductor device as follows (column 2, line 45 to column 3,
line 26):
A method for manufacturing a semiconductor device
according to a second aspect of this invention
comprises the steps of forming a groove portion whose
side surface is formed of a first insulating film and
whose bottom surface is formed of a silicon film and a
third insulating film lying around the first
insulating film on a main surface of a semiconductor
substrate on which a gate insulating film is formed;
forming a first metal film on the silicon film of the
bottom portion of the groove portion; reacting the
silicon film and the first metal film by a heat
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