Appeal No. 2005-0339
Application No. 09/376,039
deposition (HDP-CVD), over the patterned conductive layer and to
fill the gaps between conductive lines;
leaving the deposited FSG layer exposed;
chemically mechanically polishing the exposed FSG layer to
reduce the height of the peaks to a substantially uniform height;
and
depositing an undoped oxide layer on the exposed FSG layer
after the chemical mechanical polishing of the FSG layer.
The examiner relies upon the following references as
evidence of obviousness:
Lee 6,008,120 Dec. 28, 1999
Usami et al. (Usami) 6,157,083 Dec. 5, 2000
Appellants' claimed invention is directed to a method of
making an integrated circuit by depositing a fluoro-silicate
glass (FSG) layer over a patterned conductive layer on a
semiconductor substrate. The FSG layer fills the gaps between
the conductive lines and also forms peaks of non-uniform height
over the conductive lines. The FSG layer is chemically
mechanically polished to reduce the height of the peaks to a
uniform height, and then an undoped oxide layer is deposited on
the exposed FSG layer.
Appealed claims 1, 2, 4-19 and 21-28 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Lee in view of
Usami.
-2-
Page: Previous 1 2 3 4 5 6 7 Next
Last modified: November 3, 2007