Ex Parte Cecchi et al - Page 2




              Appeal No. 2005-0827                                                                                         
              Application No. 09/903,239                                                                                   

                                                    BACKGROUND                                                             
                     The invention is directed to a differential amplifier circuit that reduces the speed-                 
              limiting effects of capacitance by employing passive (rather than active) elements for                       
              biasing.  Claim 1 is reproduced below.1                                                                      
                     1.     A differential amplifier for providing common-mode rejection while                             
                     providing differential-mode amplification, comprising:                                                
                            a.      an active differential amplification element electrically coupled to a                 
                     first input signal, a second input signal and an output signal, the active differential               
                     amplification element also electrically coupled to a first voltage and a different                    
                     second voltage; and                                                                                   
                            b.      a passive bias element electrically coupled to the active differential                 
                     amplification element, the passive bias element capable of biasing the active                         
                     differential amplification element so that the active differential amplification                      
                     element operates in a saturation mode, thereby generating the output signal so                        
                     that the output signal corresponds to a voltage difference between the first input                    
                     signal and the second input signal.                                                                   
                     The examiner relies on the following references:                                                      
              Sasaki                              5,039,873                           Aug. 13, 1991                        
              Zhang                               6,313,696 B1                        Nov.  6, 2001                        
                                                                               (filed Dec.  8, 1999)                       
                     Claims 1-10 stand rejected under 35 U.S.C. § 103 as being unpatentable over                           
              Zhang and Sasaki.                                                                                            
                     We refer to the Final Rejection (mailed Mar. 5, 2004) and the Examiner’s Answer                       
              (mailed Oct. 5, 2004) for a statement of the examiner’s position and to the Brief (filed                     


                     1 We note that the claim Appendix in appellants’ principal brief contains two versions of claim 3.    
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