Appeal No. 2005-2512
Reexamination Control No. 90/006,431
a display [ChipViewer 120] coupled to said power net simulator,
said display displaying a graphical user interface including a layout
representation of said power net, the graphical user interface including
interactive tools for viewing selected portions of said power net, the layout
representation of said power net including said characteristic of said
selected portions of said power net.
E. The references
The references relied on in the rejections are:11
Mitsuhashi U.S. 5,404,310 Apr. 4, 1995
Rusu U.S. 5,598,348 Jan. 28, 1997 (filed Sep. 22,
1994)
Archer Systems, Inc., “ARCADIA User Manual -- Advanced RC Analysis and
DIAgnostic Program,” Version 1.1 (Feb. 1995), Chapters 1-7 (“Arcadia Manual”).
“RailMill™ Product Brief,” Epic Design Technology (undated) (“RailMill PB”).
“RailMill™ – Improving Reliability in Deep Submicron ICs” (undated) (“RailMill
IR”), Epic Design Technology (undated).
“Chapter 2 – RailMill Tutorial,” Epic Design Technology (Mar. 24, 1995) (“RailMill
Tutorial”).12
11 The examiner has withdrawn his reliance on two additional references: (a)
Huang U.S. Patent 5,446,676; and (b) Rugen, et al. “An interactive layout design
system with real-time logical verification and extraction of layout parasitics” (June 1988).
Ans. 3.
12 RailMill PB, RailMill IR, and RailMill Tutorial are hereinafter collectively
referred to as “the RailMill documents.”
13
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