Appeal No. 2005-2557 2
Application No. 09/204,585
Representative claim 1 is reproduced as follows:
1. A processor comprising:
a plurality of functional units; and
a register file that is divided into a plurality of register file segments, each
coupled to and associated with respective ones of the plurality of functional units,
the register file segments each implemented as an addressable array and
partitionable into global registers and local registers, the global registers being
accessible by the plurality of functional units, the local registers being accessible
by the functional unit associated with the register file segment containing the
local registers, wherein the number of global registers and the number of local
registers are programmably configurable.
The examiner relies on the following references:
Yung 5,592,679 Jan. 07, 1997
Luan et al. (Luan) 5,911,149 Jun. 08, 1999
(filed Nov. 01, 1996)
Nishimoto et al. (Nishimoto) 6,023,757 Feb. 08, 2000
(filed Jan. 30, 1997)
Claims 1-28 stand rejected under 35 U.S.C. § 103(a). As evidence of obviousness
the examiner offers Yung in view of Luan with respect to claims 1, 3-14 and 23-28, and
Nishimoto is added to this combination with respect to claims 2 and 15-221.
Rather than repeat the arguments of appellants or the examiner, we make
reference to the briefs and the answer for the respective details thereof
1 The rejections of the claims based on Luan taken alone and Luan in
view of Nishimoto have been withdrawn by the examiner [answer, page 6].
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