Appeal No. 2006-0167
Application No. 10/186,263
Invention
The invention relates to a timing abstraction and portioning strategy for
integrated circuit design. See page 1 of appellant’s specification.
Claim 1 is representative of the invention and is reproduced below:
1. A method of designing an integrated circuit, comprising:
monitoring user interaction with logical blocks during a functional design
process of an integrated circuit; and
deriving, without affecting the functional design process, indications of
timing properties during the functional design process based on the monitored
user interaction, the indications of timing properties including background
heuristics describing timing properties of the logical blocks within a hierarchy of
functional elements of the integrated circuit,
wherein the indications of timing properties are used during back end
stages to complete timing closure and verification after completion of the
functional design process.
Reference
The reference relied upon by the examiner is:
Chang et al. (Chang) 6,594,800 July 15, 2003
(filed Jan. 4, 2001)
Opinion
We have carefully considered the subject matter on appeal, the rejection
advanced by the examiner and the evidence of anticipation relied upon by the
examiner as support for the rejection. We have, likewise, reviewed and taken
into consideration, in reaching our decision, appellant’s arguments set forth in the
2
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