Appeal No. 2006-0167
Application No. 10/186,263
“without affecting functional design process” was not ignored, but rather
considered as a negative limitation and that Chang does not teach that deriving
the timing properties affects the functional design process.
Additionally, the examiner states on pages 6 and 7 of the answer:
Chang et al., column 9, lines 43-45 discloses that timing margin
specification (containing information for each circuit block) is received
from the front-end acceptance design stage as observed from Figure 8,
wherein the block named “Create Timing Environment” is fed by the
information coming from front-end acceptance design stage (column 10,
lines 44-46). Furthermore Chang et al. discloses that timing verification
can be performed during front-end acceptance design stage (column 9,
lines 60-63), which means that timing verification is produced based on
the information obtained by the front-end acceptance design stage.
We concur with the examiner. Claim 1 includes the limitation “deriving,
without affecting the functional design process, indications of timing properties
during the functional design process based on the monitored user interaction.”
We find no disclosure in Chang that suggests that the derivation of timing
indications affect the functional design process. Thus, we are not persuaded by
appellant’s arguments that the examiner ignored these limitations.
Similarly, we are not persuaded by appellant’s argument that Chang does
not teach that the timing is obtained from the front-end acceptance stage.
Appellant’s argument is not commensurate with the scope of the claim. Claim 1
includes the limitation of deriving “indications of timing properties during the
functional design process” and “the indications of timing properties are used
during back end stages to compete timing closure and verification after
completion of the functional design process.” In analyzing the scope of the claim,
5
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007