Appeal No. 2006-0167
Application No. 10/186,263
[I]n rejecting independent Claims 1, 14 and 27, the Examiner alleged that
“the timing model (timing properties of the logical blocks) is obtained from
Front-end acceptance stage (102) as a result of monitoring user
interaction with logical blocks corresponding to a hierarchy of functional
elements (col. 2, ll. 35-36, col. 10, ll. 44-46)” (emphasis added) (Office
Action 12/22/2004, page 3, lines 3-6). Applicant respectfully submits that
this allegation is not even supported by the Examiner’s own citation.
Appellant additionally argues, on page 6 of the reply brief:
However, even though the front-end acceptance stage feeds information
to a timing model according to Chang, nowhere in Chang was it taught,
disclosed or suggested that the timing model is obtained as a result of
monitoring user interaction with logic blocks. As is well known by those of
ordinary skill in the art, there are many steps included in the front-end
design state. However, the front-end design stage may or may not include
a step of monitoring user interaction with logic blocks. Thus, the fact that
the front-end acceptance stage feeds information to a timing model does
not mean that the timing model is obtained as a result of monitoring user
interaction with logic blocks, since the front-end acceptance stage may not
include the step of monitoring user interaction with logic block, and/or the
timing model may be obtained as a result of steps included in the front-
end acceptance stage other than the step of monitoring user interaction
with logic blocks.
The examiner states on page 5 of the answer:
Chang et al. discloses a method of designing an integrated circuit
using a design process based on the block-based design (BBD)
methodology including front-end acceptance design stage, such as
selecting the logical blocks for design and collecting the estimation
data for each block (column 8, lines 21-27), using a Scan Design
methodology (monitoring) (column 4, lines 2, 3) “without affecting the
functional design process” as shown on the Figure 1, wherein during the
design process, front-end acceptance design stage, not only performs
their intended functions, but also generate the information needed for
timing verification (column 9, lines 66, 67; column 10, lines 1-4).
Further, the examiner states on pages 5 and 6 of the answer that the limitation:
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