Appeal No. 2006-0537 Page 5
Application No. 09/753,766
Parady’s patent. Correspondingly, Bondi’s Figure 3 execute unit 52 appears to
detect misdirected branch instructions as claimed, thus activating a proper fetch
in instruction fetch unit 38.
As to the motivation issue, we recognize as well as the examiner admitting
that Parady does not even mention and is not specifically concerned with the
problem of latency of mispredicted branches per se. Appellants’ argument at
page 8 of the brief that without the benefit of the present application, “one skilled
in the art would only be motivated to add Bondi’s reduced latency mispredicted
branches to Parady’s system, resulting in a system with both performance
improvements” appears to admit the proper combinability of these two
references.
Correspondingly, the examiner’s best statement of the combinability issue
appears to be expressed at pages 19 and 20 of the answer which we reproduce
here, and which is somewhat repeated beginning at page 24:
Parady has taught that switch logic module detects a long latency
event in a software thread and schedules a switch to another
software thread during a latency of said long latency event (Parady
column 2, lines 18-19 and column 2, lines 27-29). Parady has even
taught that jump instructions, which are equated to branch
instructions (InstantWeb’s Free On-line Computing Dictionary
‘branch’), are long latency instructions (Parady column 4, lines 6-8).
Parady has not taught that ‘branch misprediction’ is one of his set
of long-latency events. Bondi has taught that branch misprediction
requires ‘numerous cycles…to reset the pipeline(s) to an
operational state and, thus, valuable processor cycle time is lost.’
In essence, Bondi has taught that a branch misprediction is a long
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