Appeal No. 2006-0943
Application No. 09/923,604
BACKGROUND
The invention relates to testing an integrated circuit, performing a test of the
behavior of a combinational logic system in comparison with test software emulating
the nominal behavior of the integrated circuit. Representative claim 1 is reproduced
below.
1. An arrangement for testing an integrated circuit comprising a
combinational logic system and a test circuit, which arrangement performs a test
of the behavior of the combinational logic system in comparison with test
software which emulates the nominal behavior of the integrated circuit, the
arrangement comprising:
two identical software models of the combinational logic system to be
tested, in which a test sample is applied for test purposes to a first of these
software models and whose output signals are coupled to a second of these
software models;
wherein the test circuit, in a test mode, applies a first test sample in a first
test clock cycle to the input of the combinational logic system of the integrated
circuit and receives the output signal in a buffer memory and which feeds back
this output signal as a second test sample in a second test clock cycle to the
input of the combinational logic system and again receives the output signal of
the combinational logic system in the buffer memory
wherein, at the end of the second test clock cycle, the arrangement
compares the results of the combinational logic system of the integrated circuit
in the buffer memory with the results of the second software model.
The examiner relies on the following references:
Kasuya 4,366,393 Dec. 28, 1982
Patel et al. (Patel) 5,377,197 Dec. 27, 1994
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