Appeal No. 2006-0943
Application No. 09/923,604
against the claims. Test circuit 100, according to the examiner, includes the feedback
that appellant contends to be missing. (Answer at 4.)
In view of Kasuya’s description of Figures 1 and 4, and the inputs and outputs
with respect to logic circuit 100(100') in Figure 4 as compared with the inputs and
outputs to circuit 100 in Figure 1, we consider the reference to support the examiner’s
position with respect to Figure 4. However, the reference does not support the
examiner’s position with respect to Figure 1.
Kasuya teaches that testing of an integrated logic circuit can be achieved by
utilizing a different circuit structure from that of regular operation. The feedback loop of
the sequential circuit is cut off from the combinational circuit. Random signals are used
as test input, and the group of flip-flops are used to collect the test results. Col. 2, ll.
22-29. In the embodiment of Figure 1, multiplexer 4 supplies combinational logic circuit
1 with one of the random signal from random signal generator 3 and the output YO from
register 2. Col. 3, ll. 18-28. In regular operation, register 2 operates as memory
elements for the internal conditions of circuit 100. Multiplexer 4 supplies the output YO
of register 2 as the feedback input YN of combinational circuit 1, effecting a sequential
circuit. In the testing mode, however, multiplexer 4 supplies the random signal from
random signal generator 3 to the combinational circuit 1. Col. 4, l. 44 - col. 5, l. 2.
Circuit 100 in test mode thus does not feed back the output signal to the input of
the combinational logic circuit. Test mode results are stored in feedback shift register 2
-4-
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