Appeal No. 2006-0943
Application No. 09/923,604
Ilker Hamzaoglu et al. (Hamzaoglu), Compact Two-Pattern Test Set Generation for
Combinational and Full Scan Circuits, Int’l Test Conference Proceedings, pp. 944-53,
Oct. 18-23, 1998.
Claims 1-3 stand rejected under 35 U.S.C. § 103 as being unpatentable over
Kasuya, Patel, and Hamzaoglu.
We refer to the Final Rejection (mailed Apr. 4, 2005) and the Examiner’s Answer
(mailed Nov. 2, 2005) for a statement of the examiner’s position and to the Brief (filed
Sep. 6, 2005) and for appellant’s position with respect to the claims which stand
rejected.
OPINION
The statement of the rejection against claims 1 through 3 is set forth in the Office
action mailed May 12, 2004. Appellant contests one of the examiner’s findings with
respect to Kasuya. According to the rejection, Kasuya discloses a test circuit, in a test
mode, which feeds back an output signal to the input of a combinational logic circuit.
Appellant submits that Figure 4 of Kasuya illustrates the circuit in its test
configuration, and demonstrates the lack of any feedback from the output of the logic
circuit to the input of the logic circuit. (Brief at 7.) The examiner responds that logic
circuit 100(100') in Figure 4 equates to the entirety of Figure 1, including the feedback
circuit shown in Figure 1. Test circuit 100, illustrated in Figure 1, is the circuit applied
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