Appeal No. 2006-1049
Application No. 09/667,826
37. In a preferred implementation, as illustrated in FIG. 3B, the offset
correction circuit 220 includes a plurality of parallel coupled capacitors 224.
Capacitors 224 are coupled between output node 222 and a reference node 226
maintained at an offset reference voltage VR, via respective switches 228 (col. 13,
lines 13-18).
38. Switches 228 receive the binary offset correction coefficients S0-SN
described above to select the specific capacitors 224 which are coupled into the
offset correction circuit 220 (col. 13, lines 18-21).
39. Each capacitor 224 which is coupled to node 222 by virtue of the
corresponding switch 228 being closed will subtract (or add) a voltage from (or to)
node 222 corresponding to the difference between VD and VR and the capacitance
of the capacitor 224 (col. 13, lines 21-25).
40. The respective capacitances of capacitors 224 are illustrated in FIG.
3B as C0-CN and are preferably chosen such that each capacitance is double that of
the previous capacitor in the network; i.e. the capacitance of the Nth capacitor is
2NC0. That is, the capacitors C0-CN have the following values:
C0, 2C0, 4C0 . . . 2NC0.
Thus, for example, for N=4, the offset compensation network will have 16 discrete
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Last modified: November 3, 2007