Appeal No. 2006-1686
Application No. 10/040,055
The invention pertains to the performance of layout
beautification on an integrated circuit (IC) layout. Layout
beautification is a technique for detecting and correcting a
layout imperfection. A shape-based algorithm is employed by
the layout beautification system.
Representative independent claim 11 is reproduced as
follows:
11. A method for performing a layout beautification
operation on an integrated circuit (IC) layout comprising a
plurality of polygons, the method comprising applying a first
action to a first portion of the IC layout responsive to
determining that a first shape associated with the first action
matches the first portion of the IC layout,
the first shape comprising at least a first edge and a
second edge related according to a defined property, the first
shape being configured to match a first type of layout
imperfection,
the second edge being contiguous with and substantially
perpendicular to the first edge, and wherein the first shape
further comprises:
a third edge, the third edge being contiguous with and
substantially perpendicular to the second edge;
a fourth edge, the fourth edge being contiguous with
and substantially perpendicular to the third edge; and
a fifth edge, the fifth edge being contiguous with and
substantially perpendicular to the fourth edge, wherein none of
the first edge, the second edge, the third edge, the fourth edge,
and the fifth edge are substantially side-by-side with each
other.
2
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Next
Last modified: November 3, 2007