Appeal No. 2006-1686
Application No. 10/040,055
layout, but that while these tools enable the accurate creation
of IC layouts, the rules embodied in these tools may result in
“layout imperfections.” Thus, while the results of the automated
tools may be electrically correct and optically correct, the
polygons that make up the actual IC layout might include
unintended irregularities, or “layout imperfections” which may
adversely affect layout printability or device performance. The
specification also explains how “layout beautification” is a
technique for detecting and correcting such layout imperfections.
Thus, it does appear to us that the instant specification
does, in fact, at least distinguish “layout beautification” (a
technique for detecting and correcting layout imperfections) from
OPC and DRC (automated tools used to perform various operations
on an IC layout to accurately create the IC layouts). With this
distinction in mind, while it is clear that Agrawal describes OPC
and DRC tools, it is not clear to us that Agrawal describes the
claimed layout beautification and layout imperfections.
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