Appeal No. 2006-1816
Application No. 10/386,146
Appellants’ invention is directed to a high-speed front-multiplexed repeater circuit
that limits input leakage current levels in the event one or more input voltages of the
circuit exceeds the supply voltage. The multiplexor includes a plurality of transmission
gates made of a first PMOS pass transistor and an NMOS pass transistor (specification,
page 3). The first blocking element is coupled between the supply voltage and the
back-gate nodes of the first PMOS transistors while a second blocking element is
coupled between the gate nodes of the first PMOS transistors and the source nodes of
the NMOS transistors (id.). According to Appellants, a first diode blocks the back-gate
leakage to the supply voltage and the second blocking element blocks the leakage
current paths from the differential inputs to the first PMOS transistors when the PMOS
transistor is “off” and an input voltage exceeds the supply voltage (id.). An
understanding of the invention can be derived from a reading of exemplary independent
claim 1, which is reproduced bellow:
1. A driver circuit, comprising:
a plurality of differential inputs;
at least one differential output;
a plurality of control inputs; and
a multiplexor coupled between the differential inputs and the at least one
differential output, the multiplexor being configurable by the control inputs to allow a
selected one of the differential inputs to be routed to at least one differential output, the
2
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