Appeal No. 2006-2050
Application No. 10/045,913
insulator liner is etched. Upon removal of the mask, an insulating layer is deposited in
the first and second trenches.
Claim 1 is illustrative of the invention and reads as follows:
1. A method for forming a semiconductor device structure in a semiconductor layer,
comprising:
forming a first trench of a first width and a second trench of a second width in
the semiconductor layer;
growing a first insulator liner in the first trench and a second insulator liner in the
second trench;
forming a mask over the second trench;
etching at least a portion of the first insulator liner while the mask is over the
second trench;
removing the mask; and
depositing an insulating layer in the first trench and the second trench.
The Examiner relies on the following prior art:
Koike et al. (Koike) 5,578,518 Nov. 26, 1996
Lee 5,994,201 Nov. 30, 1999
Shiozawa et al. (Shiozawa) 6,245,641 Jun. 12, 2001
S. Wolf and R. Tauber (Wolf), Silicon Processing for the VLSI Era, Vol. 1, 532-33,
(1986).
Claims 1, 2, 5, 8-10, 15, 19, 23-27, 29, and 32-34 stand rejected under 35 U.S.C.
§ 102(e) as being anticipated by Shiozawa. Claims 3, 4, 6, 16-18, 22, 28, 40, and 42
stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Shiozawa alone.
Claims 6, 16, 17, 30, and 31 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Shiozawa in view of Wolf. Claims 7, 18, 20, and 21 stand rejected
under 35 U.S.C. § 103(a) as being unpatentable over Shiozawa in view of Lee.
Claims 38-42 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over
Shiozawa in view of Koike.
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