Appeal 2006-2328
Application 10/131,049
in which the signals are previously separated into a horizontal synchronizing
signal (HS) and a vertical synchronizing signal (VS) (col. 10, ll. 30-41).
Circuit 201 separates the horizontal and vertical synchronizing signals and
unifies the polarities (col. 8, ll. 59-68). Circuit 201 also contains an
H-omission countermeasure circuit 306 for detecting a lack of a horizontal
synchronizing signal during a vertical synchronizing signal period and
supplying a pseudo-horizontal synchronizing signal (col. 10, ll. 25-29; col. 13,
l. 18, to col. 14, l. 17; Figs. 7 and 8). Circuit 201 outputs the separated
synchronizing signals to a control processing circuit 206, where "[t]he control
processing circuit 206 is constituted by use of, for example, an LSI of a
one-chip microcomputer or the like" (col. 9, ll. 6-8). "The control processing
circuit 206 judges the respective frequencies of the horizontal and vertical
synchronizing signals HD2 and VD2 fed thereto, in accordance with the
program stored in the control memory 207" (col. 9, ll. 9-12), and outputs
"control data for indicating a display size" (col. 9, ll. 18) and "control data for
indicating a display position" (col. 9, ll. 27-28) in addition to the
synchronizing signals HD1 and VD1 (Fig. 2).
Figure 9 of Arai discloses a second embodiment of the DAT 2. "In
FIG. 9, the function of the synchronizing signal processing circuit 201 of the
DAT 2 shown in FIG. 2 is executed by software of the control processing
circuit 206. FIG. 10 is a flow chart showing the processing flow of the
control processing circuit 206." (Col. 14, ll. 32-36.) As previously noted,
element 206 is a microcomputer (col. 9, lines 6-8). As shown in Figure 10,
- 6 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: September 9, 2013