Ex Parte Deaton - Page 2

                Appeal 2006-3382                                                                               
                Application 10/461,709                                                                         

                      Appellant appeals from a final rejection of claims 1, 2, 4, 5, 7, 8, 14-                 
                22, 28-51, 53-55, and 57-62 under authority of  35 U.S.C. § 134 (2002).  The                   
                BPAI has jurisdiction under 35 U.S.C. § 6(b)(2002).                                            
                      Appellant’s invention relates to a circuit for delivering high power                     
                current pulses to an electronic load in an efficient manner.  In the words of                  
                the Appellant:                                                                                 
                      The present invention comprises a scalable, interleaved pulse forming                    
                      converter having 2 Buck switching converter modules each                                 
                      contributing half to the total load of the circuit.  Synchronization                     
                      pulses to the two modules are set 180 degrees out of phase of each                       
                      other to reduce ripple current. Additional embodiments are also                          
                      claimed in which module interleaving may be utilized to further                          
                      reduce ripple current and increase power, as well as to electrically                     
                      isolate the load from input or battery ground.                                           

                      Claim 1 and Claim 57 are exemplary and representative:                                   
                      1.  A circuit for providing an electrical pulse to a load, comprising:                   
                      a.  a first Buck converter circuit;                                                      
                      b.  a second Buck converter circuit connected to said first Buck                         
                             converter circuit, each said Buck converter circuit adapted to                    
                             receive a current command signal for establishing an internal                     
                             reference voltage within each said Buck converter circuit;                        
                      c.  means for applying a voltage across said first and said second                       
                             Buck converter circuits;                                                          
                      d.  a capacitor connected in parallel with said voltage means for                        
                             reducing ripple in said voltage across said first and said second                 
                             Buck converter circuits;                                                          
                      e.  a synchronization controller operationally connected to each                         
                             said Buck converter circuit for initiating electrical pulses in                   


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