Appeal 2007-0339
Application 09/872,600
host device." (Col. 2, ll. 46-52.) The IC "provides the peripheral device
with sole access to the disk controller when operating in a straight mode.
In [the] straight mode, the peripheral device may communicate with the disk
controller through a PCI bus to perform operations, such as retrieving or
writing data to the peripheral device." (Abs. ll. 5-10.) The abstract, to
which the Examiner cites, supra, discusses isolating controllers from the
disk controller. To wit, "in [the] straight mode, other controllers, including
the host's CPU, may be prevented from using the disk controller to avoid
data collisions, data loss and possible system failure." (Id. 10-13.)
We are unpersuaded, however, that the IC isolates the other
controllers from the PCI bus. To the contrary, the reference explains that
"because IDSEL 135 is disconnected from PCI bus 115, other devices . . .
may become master of PCI bus 115 [although the other devices] cannot
detect disk controller 110 when they perform a configuration cycle."
(Col. 3, ll. 46-49.) We agree with the Appellants aforementioned argument
that "isolating the disk controller 110 from the other masters is wholly
different from 'isolating the first bus controller from the bus'. . . ." (Reply
Br. 2.)
V. CONCLUSION
Absent a teaching or suggestion of responding to a detection signal by
automatically isolating a first bus controller from a bus, we are unpersuaded
of a prima facie case of obviousness. Therefore, we reverse the rejection of
claims 1, 13, 21, 23, 35, 44, 52, and 53 and of claims 2-10, 12, 12-20, 24-31,
36-41, 45-50, 54, and 55, which depend therefrom.
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