Appeal 2007-0803
Application 10/197,801
1. A MOS transistor circuit comprising:
switching means for electrically switching a connection of a
semiconductor substrate or well in which a first MOS transistor is formed to
either a gate terminal of the first MOS transistor or a substrate voltage
terminal for the semiconductor substrate or well, wherein the switching
means comprises:
a switch having a second MOS transistor whose source and drain
terminals are connected to the gate terminal and the semiconductor substrate
or well of the first MOS transistor, respectively, and a third MOS transistor
whose source and drain terminals are connected to the substrate voltage
terminal and the semiconductor substrate or well of the first MOS transistor,
respectively,
wherein the second MOS transistor or the third MOS transistor is an
n-type MOS transistor and the other is a p-type MOS transistor, and when
the first MOS transistor is in an active state, the second MOS transistor is
turned on and the third MOS transistor is turned off to connect the
semiconductor substrate or well to the gate terminal, and when the first MOS
transistor is in a standby state, the second MOS transistor is turned off and
the third MOS transistor is turned on to connect the semiconductor substrate
or well to the substrate voltage terminal, and
wherein the gate terminals of the second MOS transistor and the third
MOS transistor are electrically connected to each other in order to receive a
switching signal for switching the first MOS transistor between the active
and standby states,
wherein an absolute value of the threshold voltage of the first MOS
transistor is set to be a lower value in the active state than in the standby
state.
The following references are relied on by the Examiner:
Hirano US 6,304,110 B1 Oct. 16, 2001
(filed October 27, 1998)
Mattison US 5,179,295 Jan. 12, 1993
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