Appeal 2007-0898
Application 09/962,786
1. A method comprising:
providing an integrated circuit having a layer of meal;
forming an on-chip decoupling capacitor stack, the on-chip
decoupling capacitor stack including,
a bottom electrode on the layer of metal;
a dielectric layer;
a top electrode separated from the bottom electrode by the dielectric
layer; and
a conductive top electrode barrier contacting the top electrode,
wherein the top electrode barrier comprises a material that is more
electrically conductive than a material for the top electrode, and
wherein the top capacitor electrode is formed on the dielectric layer
and the top electrode barrier is formed on the top electrode in a single
deposition chamber without removing the on-chip decoupling capacitor
stack from the single deposition chamber.
The Examiner relies upon the references as evidence of obviousness:
Kirlin US 5,976,928 Nov. 2, 1999
Kang US 6,180,482 B1 Jan. 30, 2001
Nozaki US 6,389,754 B2 May 21, 2002
Sze, "Physics of Semiconductor Devices," Second Edition, John Wiley &
Sons, Appendix 1, p. 852 (1981).
Shimada, "Tantalum Nitride Metal Gate FD-SOI CMOS FETs Using Low
Resistivity Self-Grown bcc- Tantalum Layer, "IEEE trans. on Electron
Device, 48, (Aug. 2001) 1619-1626.
2
Page: Previous 1 2 3 4 Next
Last modified: September 9, 2013