Ex Parte Taniguchi et al - Page 6

                Appeal  2007-0973                                                                            
                Application 10/254,835                                                                       
                generating an induced                  electromagnetic field emitted from                    
                electromagnetic force in an antenna    antenna 67 (Fig. 3) induces                           
                belonging to a tag;                    electromagnetic force (emf) in patch                  
                                                       antenna 62 of IC card (tag) 61; col.                  
                                                       2, ll. 32-46                                          
                providing electric power to said tag;  electric power is provided to the tag                 
                                                       by circuit 22b (Fig. 1) in                            
                                                       transmit/receive circuit 63 (Fig. 3);                 
                                                       col. 1, ll. 16-32; col. 3, ll. 20-29                  

                relaying said electromagnetic force    the emf is relayed to demodulator                     
                to a demodulator circuit through an    circuit 22a (Fig. 1) through                          
                impedance matching circuit;            impedance matching circuit 2, 3, 9,                   
                                                       both circuits residing in                             
                                                       transmit/receive circuit 63; col. 2, l.               
                                                       54 - col. 3, l. 19                                    

                demodulating said electromagnetic      the emf is demodulated by                             
                force;                                 transmit/receive circuit 63 (Fig. 3)                  
                                                       and relayed to CMOS logic circuit                     
                                                       64                                                    

                decoding a data signal resulting       the demodulated signal is decoded by                  
                from said demodulating; and            CMOS logic circuit 64, which                          
                                                       separates a clock and data from the                   
                                                       signal received from transmit/receive                 
                                                       circuit 63 through terminal 10 (Fig.                  
                                                       1); col. 3, ll. 15-17                                 


                storing data from within said data     CMOS logic circuit 64 stores the                      
                signal into a storage circuit.         data to memory 65; col. 2, ll. 44-46                  



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