Appeal 2007-1250
Application 10/458,537
Appellants' invention relates to a method and system used to design
and test circuitry, including timing analyses, such as static timing analysis
techniques (Specification 1: 4-6). Claim 1 is illustrative of the claimed
invention, and it reads as follows:
1. A method, comprising:
receiving initial static timing environment data associated with a
circuit; and
generating a data file including a plurality of all possible sources of a
generated clock included in the circuit.
The prior art reference of record relied upon by the Examiner in
rejecting the appealed claims is:
Daga US 6,877,139 B2 Apr. 05, 2005
Claims 1 through 27 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Daga.
We refer to the Examiner's Answer (mailed August 28, 2006) and to
Appellants' Brief (filed June 16, 2006) and Reply Brief (filed October 11,
2006) for the respective arguments.
SUMMARY OF DECISION
As a consequence of our review, we will reverse the anticipation
rejection of claims 1 through 27.
OPINION
Appellants contend (Br. 10) that Daga discloses generating timing
constraints, but fails to disclose the claimed data file including a plurality of
2
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